The present invention relates to the art of preparing high performance semiconductor memory devices, and, in particular, those which may experience pattern collapse as a result of having high aspect ratio TiN structures formed thereon.
Since the invention of the integrated circuit in or about 1958, etching has been an important technology to the semiconductor industry. More recently, with advent of memory devices scaled down to below 50 nanometers, high aspect ratio (HAR) structures present a challenge to the manufacture process of semiconductor memory devices. In particular, a phenomenon known as pattern collapse occurs when forming several inorganic patterns on a substrate in parallel. Pattern collapse occurs when adjacent patterns deform so as to lean on one another, or, indeed, break down or become damaged when drying in the presence of a rinse liquid used after pattern formation. The force causing pattern collapse results from capillary forces which occur during the drying phase after rinsing by the rinse liquid. Thus, when the rinse liquid is removed in the drying step, stress resulting from capillary forces acting on the patterns causes collapse.
Various techniques and chemistries have been tried to prevent pattern collapse sufficiently to enable the manufacturers to fabricate the high aspect ratio structures by, e.g., conventional wet etching processes, and then rinsing and drying to prepare the devices for use. One body of technology relates to treating high aspect ratio containing substrate surfaces with a silylating agent.
For example, United States Published Patent Application US 2011/0195190 A1 (“190 Publication”) discloses a surface treatment using a treatment liquid containing a silylating agent and a hydrocarbon non-polar solvent. The technique disclosed in the '190 Publication claims to be an improvement over a vapor treatment with a silylating agent as disclosed in Japanese Unexamined Patent Application, Publication No. S60-25231 and Japanese Unexamined Patent Application, Publication No. 2007-19465. It claims to be a further improvement of the technology disclosed in Japanese Unexamined Patent Application, Publication No. H6-163391 and Japanese Unexamined Patent Application, Publication No. H7-142349. See also non-patent reference “Proceedings of FPIE”, Volume 5754, pp. 119-128 (2005).
Further in this regard U.S. Patent Published Application US 2011/0073011 A1 (“'011 Publication”) discloses a surface treatment agent which includes a silyation agent containing at least one compound having a disilazane structure and a solvent containing a five- or six-membered ring lactone compound. The '011 Publication also refers to Japanese Unexamined Application, Publication No. H11-511900 for its disclosure of a silyation treatment using hexamethyldisilazane (HMDS). Problems concerning effective treatment using HMDS are claimed to have been overcome by using a silyation agent having a disilazane structure and a solvent containing a five- or six-membered ring lactone compound.
U.S. Published Application US 2011/0118494 A1 (“'494 Publication”) claims to overcome problems associating with treatment of TiN or SiN using a cyclic silazane compound. The treatment disclosed in the '494 Publication includes an organic solvent capable of dissolving the cyclic silazane compound but which does not react with the compound and causes little or no damage to the substrate surface which is treated.
Further with respect to this technology, published U.S. Application No. US 2011/0054184 A1 (“'184 Publication”) discloses conducting a silyation treatment on the surface of a semiconductor substrate using an agent which includes a silyation agent and a silylated heterocyclic compound. The silylated heterocyclic group included in such compound is preferably a silylated nitrogen-containing heterocyclic compound which is characterized as having aromaticity. Solvents which can be used in the treatment disclosed in the '184 Publication are those solvents which are also set forth in the '494 Publication.
U.S. Pat. No. 7,977,039 B2 (“'039 Patent”) discloses a rinse treatment for cleaning a substrate after an exposed pattern thereon has been subjected to developing treatment. The method of the '039 Patent include supplying pure water onto the substrate to clean the substrate, followed by supplying a first rinse solution composed of a surfactant with a predetermined concentration and thereafter supplying a second rinse treatment composed of a surfactant with a concentration lower than that of the first rinse solution.
Thus, while there have been several attempts at providing methods and compositions for preventing pattern collapse, the present invention provides an intermediate process step and composition for use between the cleaning and the final rinse/dry step to prevent pattern collapse of high aspect ratio TiN structures semiconductor devices.